Linearity of Toroid and Integrator Module

The plot below is of the voltage level coming out of the ADC output of the integrator module, versus the amplitude of the signal sent throught the toroid test loop -- effectively testing the linearity of the entire system. The input signal varied in amplitude from 0 to 100mV, and had a sinusoidal shape (single pulse) with a half width of 2.9 mS. (a 100 mV input signal corresponds to a charge of 3.6e13 protons) The small rectangles are the datapoints, and their size indicates the jitter of the output signal. The jitter is just over 1% for an input charge of 5e12 protons.

Despite the fact that Toroid A has a higher gain in this plot, toroid B actually has a slightly larger peak signal coming out of the integrator. (see Comparing Toroid A and B in spice) The droop due to Toroid B's shorter L/R time (it has a smaller self inductance than toroid A) significantly reduces the signal before it gets digitized. This droop will cause any jitter in the integrator trigger time to be translated into a jitter in the output voltage.

Fitted Line Parameters:

Toroid          Slope              Offset
------      --------------     ----------------
  A         43.04 +/- 0.04     -0.115 +/- 0.002
  B         36.41 +/- 0.07     -0.121 +/- 0.003

The offset is caused by small DC offsets in the op-amps in the integrator board.