Evolving Towards The
Note: This material is from a 1994(!) Talk about CCDs - the physics
remains the same, only the detector size has increased since then.
Characteristics of an Ideal Detector:
- 100% QE
- Perfectly Uniform Response
- Unlimited Dynamic Range
- Completely Understandable Characteristics
Why Astronomers Love CCDs:
- High QE compared to photographic media
- High Linearity
- Large Dynamic Range
- Fairly Uniform Response
- Relatively Low Noise
- Its Digital !
Most of these limitations have now been overcome and have lead
to todays 2048x2048 CCD detector.
Charge-coupled devices (CCDs) have been moving closer to becoming
an ideal detector and are almost there now
- Low areal coverage
- poor blue response
- Read Out Noise Dominated for Spectroscopy
- Low light level deferred Charge Transfer Problems
- Conceived in 1970 at Bell Labs
- Electronic Analogue to Bubble Memory --> a bit = packet of charges
(e-) or holes (h+)
- Charge detection amplifier gives an external voltage
- Charge packets read one at a time --> Serial Device
- 1973: JPL initiates Scientific Grade large array CCD program
Fairchild 100x100 on an 8-inch telescope produces first astronomical
- 1974--1979: NASA's Traveling CCD Camera System --> always made
new scientific discoveries
- 1979: RCA 320x512 LN Cooled System sees first light at KPNO 1-m
THEORY AND OPERATION:
- Main limitation is number of gate shorts or opens. These
defects are usually caused by contamination. Minimum clean room
level is 100.
- Kinds of shorts
- Frontside Illumination:
- Limited by absorption of blue photons by relatively thick
(5000 A) poly-silicate gates. Absorption depth for 4000 A photon is
only 2000 A. Also, surface reflectivity increases with decreasing
wavelength. Hence thick frontside illuminated devices have good QE
only in the red.
- Backside Illumination:
- Thin the substrate from 300 microns down to about 10 microns. (this
took about a decade to learn how to do it)
- QE is much better in backside illuminated devices
- Thinning process was non-uniform, corners thinner than the center -->
leads to serious nonuniform response (the potato chip factor)
- non-flatness produced poor focus when illuminated with beams
faster than f5
- After thinning the silicon oxides forming a native oxide layer
about 20 A in thickness which, through a process too complex to be
understood by astronomers, causes the surface to become positively charged.
- For high and stable QE the backside of the CCD must be negatively
charged to drive signal electrons towards the front surface. Three
- UV flooding --> creates lots of free electrons. Some of these
electrons have enough energy to escape to the back surface thus creating
a small surface voltage which in turn attracts and acculumates a
thin layer of holes; hole gradient sets up
an intense electric field in the silicon (100,000 V/cm). But, doesn't
last unless the detector stays at -95 C (or lower).
- Flash Gates --> deposit mono-atomic layer of gold or platinum;
causes silicon electrons to tunnel through the native oxide layer
and generate a surface potential equal to the work function difference
between the metal and the silicon. Unfortunately, in a vacuum positive
charge is observe to buildup in the native oxide layer. So invent,
biased flash gate - now you have a shutter and control of the QE!
Positive bias, charge is swept towards the backside - no QE; negative
bias, charge is swept to the frontside --> lots of QE
- Boron doping --> ion implants provide a permanent hole layer (i.e.
thin layer of hole accumulation).
Manufacturing process requires heating of the device to anneal the damage
down during the implantation process. This is best accomplished using
a scanning high energy pulsed laser directly on the immediate backside
- Phosphor Coatings:
- Converts incoming UV photons to longer wavelength photons.
- QE Notches
- Can evaporate under conditions of high vacuum.
- Scattering of light from Target pixel to adjacent pixels in the UV
--> mostly a problem for front illuminated devices as on the backside
the phosphor is in direct contact with the silicon separated only by
the thin native oxide layer
- multiple e-h pair generation is not possible; Phosphor only
emits one visible photon per incoming photon
But for transfer rates of less than 100 kpixels/sec, theory doesn't matter
and CTE is limited by four other factors that are all related to electron
traps within the device:
- CTE -- theoretically limited by three effects
- self-induced drift --> caused by mutual electrostatic repulsion
of the carriers within a packet; dominates for large packets
- thermal diffusion
- fringing field For Roger
Design Traps --> narrowing of signal channel which produces a
potential barrier in which charge can be trapped. Usually happens at
transfer gate between array and the horizontal register as transfer
gates are tapered in order to properly transfer charge to the horizontal
register. Hence a trap (potential barrier) is created at the front of
the gate. This is most noticeable when low-level point sources are
imaged. As the packet passes through the transfer gate, the charge
is redistributed into a "tail" of trailing pixels. This is fatal for HST
detectors. Problem is temporarily solved by a fat-zero which fills the
trapping regions thus allowing signal charge to pass through unimpeded.
But this increases the read noise of the detector. Note, about 50,000
HST CCDs were fabricated and tested before this problem was noticed
and characterized. Now CCDS are designed so that the signal carrying
channel is constricted at the end of beginning of the transfer gate as
opposed to mid-phase.
Process Induced Traps --> Localized Defects which are usually
randomly distributed. Okay if the defect is in a vertical column but
is fatal if its in the horizontal register. This traditionally has
been a main cause of low sensor yield.
Bulk Traps --> lattice defects or deep-level metallic impurities
in the substrate. If these traps lie in the charge transfer channel
then trapping occurs. Ultimately, CTE is bulk state limited. Bulk
traps usually become active at low operating temperature when emission
time constant of the trap is equal to the charge transfer time from one
phase to the next. So, speed up this time either by operating at
higher temperature or adjusting clockrates.
Radiation Induced Traps: Energetic particles displace silicon atoms
from the lattice structure. These then act like bulk traps. This
is mostly a problem for space based CCDs.
Testing CTE --> this is kind of Cool
- Use Fe-55 which produces a 5.9 Kev photon. When this interacts
with the CCD, 1620 electrons are generated in a volume much smaller
than a pixel. Then see if 1620 electrons come out of your amplifier.
For a 2048x2048 and a CTE of .999999, 41 electrons will be lost and
this, in fact, can be measured now!
- On-chip Amplifier Noise: combination of thermal white noise,
1/f noise and sense node sensitivity.
- Sense node is the final collecting point at the end of the
horizontal register. This converts charge to voltage. Typical sensitivities
are 1--4 microvolts per electron
- Voltage to outside world = charge/capacitance
- White and 1/f noise depend on amplifier size (getting lower with
larger sizes). But, as amplifier size grows its input capacitance (input
comes from the sense node) also grows which lowers sense node sensitivity
and increases the net read noise
- After a decade of experimentation, optimal design was reached and
typical readout noise is now 4-5 electrons (full well capacity is at
least 100,000 electrons these days).
- Note that 1/f noise is thought to be associated with surface
states and therefore should be absent in buried channel CCD amplifiers,
but its not. This is a mystery
- Generated where current channel does interact with the surface
(maybe within the amplifier electronics)
- Note that if 1/f noise were not present, white noise could go to
zero just by increasing the electrical bandwidth of the CCD signal
processor and increasing the sampling period for each pixel.
- Still the current world record is 1.5 electrons rms !
DARK CURRENT NOISE:
Thermal generation of electrons by the finite temperature of the device.
Surface dark current is 2--3 orders of magnitude higher than the
bulk dark current. Surface dark current depends on:
- Thermal generation and diffusion in the bulk
- in the depletion region
- in the surface states at the Si-SiO(2) interface
After Two Decades of R&D, CCDs aren't quite the perfect detector
but they are PFG (e.g. damn close)
The Electronic Universe Project